Why does a MOSFET with a Small Internal Resistance Heat Up?

Hello everyone, I am Rose. Welcome to the new post today. Today I will introduce the types of breakdown in MOSFET,how tomeasure MOSFET power loss and other questions.

Ⅰ.  What are the types of MOSFET breakdowns?

Let us discuss the test conditions. The drain voltage is scanned until the current at the Drain terminal exceeds 1uA, after which all the source and gate substrates are grounded. Drain to source.  Drain to Bulk, and Drain to Gate are the three leakage routes in terms of device structure.

1. Drain->Source punch-through breakdown

This is due to the depletion zone of the Drain  /Bulk PN junction expanding when the reverse bias voltage is applied to Drain,  Punch-through occurs when the depletion region strikes the source and forms a path between the source and the drain without opening ( punch through).

So, how do you avoid punch-through? This is related to the diode's reverse bias characteristic. The breadth of the depletion region is proportional to both the voltage and the doping concentration on both sides. The wider the depletion region can be inhibited as the concentration increases.: AnTI Punch Through), keep in mind that it must also play the same type of specis.

Naturally, the BV that really encountered WAT ran, and it was verified that it was no longer present on the Source side. It could also depend on whether the issue is with the width of PolyCD, Spacer, or LDD IMP.

Is it possible to rule it out? It depends on whether both  NMOS  and  PMOS  are active. Poly-related WAT can be used to verify POLY CD.

The following traits are associated with punch-through breakdown:

(1) The punch-through breakdown has a soft breakdown point. The current has the property of progressively growing during the breakdown process. Because the depletion layer increases and generates a huge current, this happens.

A high spread of the depletion layer, on the other hand, is prone to the DIBL effect, which causes the source-substrate junction to be forward biased with a progressive increase in current.

(2) The source and drain depletion layers meet at the soft breakdown point of punch-through breakdown. The carriers at the source end are injected into the depletion layer at this point and are propelled to the drain end by the electric field in the depletion layer.

As a result, the current during the punch-through breakdown has a strong rise point, which differs from the current during the avalanche collapse. During the reverse breakdown of the PN junction, the current during the breakdown is primarily the avalanche current.

(3) Punch-through failure does not always result in destructive failure. A huge number of electron-hole pairs will not be formed because the punch-through breakdown field intensity does not surpass that of avalanche breakdown.

(4) Punch-through breakdown occurs mostly in the channel body; the channel surface is not susceptible to punch-through. This is because the channel injection causes the surface concentration to be higher than the concentration. As a result, the  NMOS tube generally prevents punch-through injection.

(5) Because the concentration near the beak's edge is typically higher than that in the middle of the channel, punch-through breakdown occurs in the middle.

(6) The punch-through breakdown is affected by the length of the polycrystalline gate. The breakdown rises as the gate length grows. In a strict sense, it has an effect on avalanche breakdown as well, but it isn't as substantial.

2. Drain-》Bulk avalanche breakdown

The avalanche breakdown of the PN junction is what this is. The major reason for this is that under the reverse bias voltage of the drain, the depletion zone of the PN junction is extended, and the reverse bias electric field is applied to the reverse bias of the PN junction, forcing the electrons to accelerate and strike the lattice. New electron-hole pairs (Electron-Hole pairs) are created, and then the electrons continue to collide, causing the avalanche to multiply and lead to breakdown. As a result, the current of this breakdown rises practically vertically, making it very easy to burn. (Not to be confused with the source-drain punch-through breakdown.)

So, how can this juncTIon BV be improved? To prevent collisions from forming electron-hole pairs, the electric field in the depletion area must be decreased, owing to the features of the PN junction itself. Because it is difficult to reduce the voltage, the breadth of the depletion region can only be extended, requiring a modification in the doping profile. This is why the Abrupt juncTIon's breakdown voltage is lower than the Graded JuncTIon's.

There is, of course, the doping concentration in addition to the doping profile. The depletion region narrows with increasing concentration, hence the lower the breakdown voltage, the stronger the electric field strength. There is also a rule that the concentration on the lower concentration side has a greater impact on the breakdown voltage since the depletion region is wider.

BV=K*(1/Na+1/Nb) is the formula. The calculation also shows that if the concentrations of Na and Nb differ by ten times, practically one of them can be ignored.

Check your Source/Drain implant if the BV decreases during the real procedure and it is established that it is caused by the junction.

3. Drain-》Gate breakdown

This is primarily due to the Overlap between the Drain and the Gate.  which causes the gate oxide layer to collapse. This looks a lot like the GOX breakdown. Of course, it's more like a GOX breakdown of the Poly finger, so he'll have to be extra careful with the poly profile and sidewall damage. Of course, another issue with this Overlap is GIDL, which will contribute to BV reduction by causing leakage.

The breakdown of the MOSFET has three channels, as seen above. The first two are usually the BV cases.

The above describes breakdown in the off-state when the Gate is 0V, but when the Gate is turned on, the voltage delivered to the Drain can be too high, causing breakdown. On-state breakdown is what we call it.

This happens most frequently when the gate voltage is low or the tube is newly turned on, and it is virtually always NMOS. As a result, we normally WAT BVON as well.

Ⅱ.  How to deal with the serious situation of small current heating of mos tube?

MOS tubes are unavoidable when designing power supplies or driving circuits. MOS tubes come in a variety of shapes and sizes, as well as various uses. Of course, the switching function of a power supply or drive is used.

The working principle is largely the same whether the MOS tube is N-type or P-type. The voltage provided to the gate of the input terminal regulates the current of the drain of the output terminal in the MOS tube.

A voltage-controlled device, the MOS tube. The device's properties are controlled by the voltage provided to the gate, and the charge storage effect generated by the base current when the triode is switched is avoided. As a result, the MOS tube's switching speed should be faster than that of triodes in switching applications.

The PDF characteristics of MOS tubes are frequently examined. The RDS(ON) parameter is used by MOS tube makers to define the on-resistance. RDS(ON) is also the most significant device feature for switching applications.

RDS(ON) is defined in the datasheet in relation to the gate (or drive) voltage, VGS, and the current flowing through the switch, yet RDS(ON) is a relatively static characteristic for adequate gate drive. The always-on MOS tube is simple to heat up. Furthermore, gradually increasing junction temperature will result in a rise in RDS (ON).

The thermal impedance parameter, which is defined as the MOS tube package's semiconductor junction heat dissipation capabilities, is specified on the MOS tube datasheet. The thermal resistance from junction to case is the most basic definition of RJC.

1. The reason for the small current heating of the mos tube:

1) The circuit design problem: making the MOS tube work in a linear working state rather than in a switching state, which is one of the reasons for the MOS tube's heat.

The G-level voltage of an N-MOS switch is a few V higher than the power supply to be fully turned on, whereas the G-level value of a P-MOS switch is the reverse. It is not fully turned on, and the voltage drop is too large, resulting in power consumption; the equivalent DC impedance is relatively large, and the voltage drop increases, so U*I increases, resulting in heat generation; and the voltage drop increases, so U*I increases, resulting in heat generation. This is the most dreaded error in circuit design.

2) The frequency is too high: The major reason is that the volume is sometimes sought excessively, resulting in an increase in frequency and an increase in the loss on the MOS tube, resulting in increased heat generation.

3) The heat dissipation design is insufficient: the current is too high, and the nominal current value of the MOS tube demands good heat dissipation. As a result, if the ID is less than the maximum current, it may generate significant heat, necessitating the use of additional heat sinks.

4) The MOS tube selection is incorrect: the power assessment is incorrect, and the internal resistance of the MOS tube is not fully considered, resulting in a switch impedance increase.

2. How to solve the serious heating of mos tube with small current:

(1) 0 Do a good job in the heat dissipation design of the MOS tube, and add enough auxiliary heat sinks.

(2) Apply heatsink.

Ⅲ.  Why can the MOSFET prevent the power supply from being reversed?

The circuit will be damaged if the power source is reversed, although this is an unavoidable situation. To achieve the goal of not being destroyed even if the power source is reversed, we must add a protection circuit to the circuit.

In most cases, it can be remedied by connecting a diode to the positive pole of the power source,  however, due to the diode's voltage drop, the circuit will suffer excessive losses, especially in the case of battery power. V, significantly reducing battery life.

The advantage of using MOS tubes for anti-reverse connections is that the voltage drop is negligible. The current MOS tube can have an internal resistance of several milliohms if the internal resistance is 6.5 milliohms, the current passing through is 1A (which is already a big current), and the voltage drop is just 6.5 millivolts.

People have gradually begun to employ MOS tubes to prevent reverse power connections as MOS tubes become cheaper.

1) NMOS tube to prevent reverse power supply circuit:

Figure. 1

When properly connected:

The parasitic diode of the MOS tube is turned on shortly after the power is turned on, thus the potential of S is around 0.6V and the potential of the G pole is VBAT. Because VBAT-0.6V is higher than UGS's threshold voltage, the MOS tube's DS will be turned on. The parasitic diode is short-circuited, and the voltage loss is nearly zero, due to the low internal resistance.

When the power is reversed:

UGS=0, the MOS tube will not be turned on, and the loop with the load will be broken, thus ensuring the safety of the circuit.

2)  PMOS tube to prevent reverse power supply circuit:

Figure. 2

When properly connected:

The parasitic diode of the MOS tube is turned on shortly after the power is turned on, and the power supply and the load form a loop, resulting in the potential of the S pole being VBAT-0.6V and the potential of the G pole being 0V, the PMOS tube being turned on, and the current flowing from D to S short-circuiting the diode. 

When the power is reversed:

The G pole is at a high level, and the PMOS tube is not turned on. Protect the circuit safety.

Connection skills: Tube NMOS The negative pole of the PMOS tube is connected to DS. The parasitic diode's direction is pointed towards the right connection current direction, and DS is linked to the positive pole.

Do you have a "reverse" DS flow? Friends with keen eyes will notice that the current direction of DS in the anti-reverse circuit is the polar opposite of the current direction we normally employ.

Why turn it inside out? The UGS can meet the threshold criteria using the parasitic diode's conduction effect when the power is just turned on.

Why can it be reversed? If it's a triode, NPN can only go in one direction: C to E, and PNP can only go in one direction: E to C. One of the differences between the triode and the MOS tube is that the D and S of the MOS tube are interchangeable.

Ⅳ.  MOSFET power loss measurement

The switching loss test of MOSFET/IGBT is a vital link in power supply troubleshooting, but many engineers still rely on perceptual cognition of manual computation to measure switching loss, and the switching loss of PFC MOSFET can only be dependent on word-of-mouth experience. After repeated exploration, how to quantify the evaluation?

1. Schematic diagram and measured diagram of power loss

The schematic diagram of the switching tube's power loss is presented in Figure 3 in general. The "on process" and "off process" indicate the majority of the energy loss, with the "on state" reflecting only a minor portion of it. The loss is so negligible that it can be overlooked.

                               

Figure. 3

The actual measurement waveform is generally shown in Figure 4:

Figure. 4

2. The test difference between MOSFET and PFC MOSFET

Because the voltage and current waveforms of different cycles are nearly identical in typical MOS tubes, the overall power loss can be evaluated arbitrarily for one cycle.

Because the voltage and current waveforms of different cycles differ for PFC MOS tubes, accurate power loss estimation requires waveform capture for a long time (usually greater than 10ms) and a higher sampling rate (recommended 1G sampling rate). The recommended storage depth is greater than 10M, and all raw data (which cannot be sampled) must be included in the power loss estimate. Figure 5 shows the measured screenshot.

Figure. 5